1. Field of the Invention
The present invention relates to a drive circuit, particularly to the drive circuit of a display device using a capacitive load.
2. Description of the Related Art
FIG. 18 is a diagram showing a basic structure of a plasma display panel device. A control circuit unit 1801 controls an address driver 1802, a common electrode (X electrode) sustain circuit 1803, a scan electrode (Y electrode) sustain circuit 1804, and a scan driver 1805.
The address driver 1802 supplies a predetermined voltage to address electrodes A1, A2, A3, . . . . Hereinafter, the address electrodes A1, A2, A3, . . . are referred to individually or collectively as an address electrode Aj, the j meaning a subscript.
The scan driver 1805 supplies a predetermined voltage to Y electrodes Y1, Y2, Y3, . . . , in accordance with controls of the control circuit unit 1801 and the Y electrode sustain circuit 1804. Hereinafter, the Y electrodes Y1, Y2, Y3, . . . are referred to individually or collectively as a Y electrode Yi, the i meaning a subscript.
The X electrode sustain circuit 1803 supplies the same voltages to X electrodes X1, X2, X3, . . . respectively. Hereinafter, the X electrodes X1, X2, X3, . . . are referred to individually or collectively as an X electrode Xi, the i meaning the subscript. The respective X electrodes Xi are connected to each other and have the same voltage level.
In a display region 1807, the Y electrodes Yi and the X electrodes Xi form rows extending parallelly in a horizontal direction, while the address electrodes Aj form columns extending in a vertical direction. The Y electrodes Yi and the X electrodes Xi are arranged alternately in the vertical direction. Ribs 1806 have stripe rib structures placed between the respective address electrodes Aj.
The Y electrode Yi and the address electrode Aj form a two dimensional matrix of row i and column j. A display cell Cij is formed by an intersection point of the Y electrode Yi and the address electrode Aj as well as the adjacent X electrode Xi corresponding thereto. This display cell Cij corresponds to a pixel, and the display region 1807 can display a two dimensional image.
FIG. 19A is a view showing a cross-sectional structure of the display cell Cij in FIG. 18. The X electrode Xi and the Y electrode Yi are formed on a front glass substrate 1911. Thereon, there is deposited a dielectric layer 1912 for insulating against a discharge space 1917, and further thereon there is deposited an MgO (magnesium oxide) protective film 1913.
Meanwhile, the address electrode Aj is formed on a rear glass substrate 1914 disposed opposing to the front glass substrate 1911, thereon a dielectric layer 1915 is deposited, and further thereon a phosphor is deposited. In the discharge space 1917 between the MgO protective film 1913 and the dielectric layer 1915, Ne+Xe Penning gas and the like is sealed.
FIG. 19B is a view explaining a capacitance Cp of an AC plasma display. A capacitance Ca is a capacitance of the discharge space 1917 between the X electrode Xi and the Y electrode Yi. A capacitance Cb is a capacitance of the dielectric layer 1912 between the X electrode Xi and the Y electrode Yi. A capacitance Cc is a capacitance of the front glass substrate 1911 between the X electrode Xi and the scan electrode Yi. A sum of these capacitances Ca, Cb, and Cc determines the capacitance Cp between the electrodes Xi and Yi.
FIG. 19C is a view explaining a light emission of the AC plasma display. On an inner surface of ribs 1916, phosphors 1918 of red, blue, and green are arranged and coated in stripes of respective colors, and the phosphors 1918 are to be exited by a discharge between the X electrode Xi and the Y electrode Yi to generate light 1921.
FIG. 20 is a structural diagram of one frame FR of an image. The image is formed at, for example, 60 frames/second. One frame FR is formed by a first sub frame SF1, a second sub frame SF2, . . . , and a n-th sub frame SFn. The n is for example 10 and corresponds to the number of tone bits. Hereinafter, the sub frames SF1, SF2 and the like are referred to individually or collectively as a sub frame SF.
Each sub frame SF is constituted with a reset period Tr, an address period Ta, and a sustain period (sustained discharge period) Ts. In the reset period Tr, a display cell is initialized. In the address period Ta, each display cell can be selected to be lighted or not lighted by an address discharge between the address electrode Aj and the Y electrode Yi. In the sustain period Ts, a sustain discharge is performed between the X electrode Xi and the Y electrode Yi of the selected display cell and a light emission is carried out. The number of the light emissions (time) by the sustain pulse between the X electrode Xi and the Y electrode Yi are different in the respective SF. Hereby, tone values can be determined.
In the following Patent Document 1, there is described a plasma display device controlling the number of sustain discharges per line in order to prevent a luminance difference between the lines due to a load.
[Patent Document 1] U.S. Pat. No. 6,100,859 (Japanese Patent Application Laid-Open No. Hei 9-68945)